MATLAB Based Toolbox for Phased Array Antenna Design and Analysis

Regarding my previous project (MATLAB version of the “Arraytool”, which is not open source)

When I was an undergraduate, I had this wonderful opportunity to study a book by “E. C. Jordan & K. G. Balmain”. The book was Electromagnetic Waves And Radiating SystemsIt introduced me to a wonderful world of radiation, fields, antennas and so many other things. But one thing that really attracted me was the concept of analysis and synthesis of antenna arrays. Though the theory provided on antenna arrays in that book is not of advanced level, it gave me an insight into this beautiful world of imaginary electromagnetic waves trying to co-ordinate (interfere) with each other so that they can fulfill their assigned  jobs (like scanning or adjusting side lobes, etc).

But unfortunately to analyze even a very simple array, I had to do cumbersome array factor evaluations to finding pattern nulls, gain, etc. I am not saying that those calculations were useless. As a matter of fact, those manual computations give us very interesting insight into concepts such as grating lobes, side-lobe level, etc. However, human brains have their limitations. So, as the number of array elements increases, we need to use computer for all those numerical calculations.

However, we don’t have proper tools to educate students (or engineers) on this topic. Yes, we do have CAD tools such as HFSS, CST, ADS, etc … and they are very helpful for a microwave engineer. But, a devoted tool providing all possible solutions for antenna arrays is not available at this moment.

So, I decided to create a GUI program based on MATLAB which can answer at least some of the very important issues related my favorite topic. This project is still under construction like all my other projects … 🙂


At the time of writing this post, I was not aware of the following tools which also deal with phased array antenna design:

Anyhow, here are some screen-shots of the “partially completed program” :

Grating-Lobe Analysis (Circular Pyramidal Scan)
Grating-Lobe Analysis (Rectangular Pyramidal Scan)

For further information regarding Grating Lobe Analysis, click here.

A simple linear Taylor array (rectangular radiation pattern)
A simple linear Taylor array (rectangular radiation pattern)

For further information on Generalized Discrete Taylor & Bayliss Distribution, click here.

A simple linear Dolph-Chebyshev array (polar radiation pattern)
Pattern-Multiplication shown in rectangular plot
Pattern-Multiplication shown in polar plot
Radiation pattern cuts (Theta & Phi) in UV-domain
Contour as well as 3D patterns corresponding to a linear array
Contour as well as 3D patterns corresponding to a planar array (Circular Taylor)
Pattern corresponding to a given arbitrary array excitation I/P
Shaped beam Synthesis (here, using simple Woodward-Lawson method)
Shaped beam Synthesis (here, using simple Woodward-Lawson method)

My Verilog Workflow … III

In my previous post, I mentioned about integrating Cocotb with GNU Radio. This opens up a lot more opportunities in terms of testing DSP related Verilog modules. Have a look at the “gr_test” generator in

So, my flow right now is

  1. write Verilog module with Verilator linting ON
  2. test the Verilog module’s functionality by “writing” small test-bench(es) using “SymbiYosys” cover statement(s) and view the generated .vcd file(s) in GKWave
  3. Formally verify the module using SymbiYosys (if needed)
  4. write Cocotb test-bench to compare Verilator and GNU Radio results, and pass the test if the results agree with each other

My Verilog Workflow … II

This is in continuation to my previous post:


Recently I have come across a python library called cocotb that provides a COroutine based COsimulation TestBench environment for verifying VHDL and SystemVerilog RTL using Python. The advantages of using cocotb seem to be the following:

  • Using cocotb, one can write testbenches in Python which can be simulated in a simulator of your choice (e.g., Icarus Verilog, Verilator, Modesim, VCS, etc.). A complete list of supported simulators can be found here. I would like to use Verilator as my main simulator.
  • Compared to Verilator, generating VCD traces is much easier using cocotb. Just add VERILATOR_TRACE := 1 to the Makefile (this may change in the future as VERILATOR_TRACE will be deprecated!).
  • Though I enjoy using C for embedded systems, C++ was never my cup of tea. If I have to cross verify my Verilator simulations with some Golden Reference, I would rather write that Golden Reference in Python.
  • If I can create the Golden Reference using GNU Radio, then it would be even more fun! This will be the topic of my next blog post.
  • cocotb can generate WaveDrom JSON files on the fly … 🙂 Who doesn’t like it?
  • Using cocotb, we don’t need to worry too much about maintaining Make and CMake files that I was using in my previous workflow (though I still need to use one top-level Makefile for cocotb).


Sometimes, we would like to see how submodules are interconnected to form our main module (e.g., RTL Viewer in Quartus). netlistsvg can be a simple substitute for RTL Viewer which uses Yosys‘s JSON output to export RTL view. A demo of netlistsvg can be seen here.

SymbiYosys for Writing Simple Testbenches

We know that Symbiyosys helps us formally proving our modules. But, it can also be used to create testbenches using just one or two lines as shown below:

reg [3:0] f_clk_cnt = 0;
always @(posedge i_clk)
    `ASSUME(i_ce && i_rstn);
    if (counter == (HALF_CLOCK_STRECH-1)) f_clk_cnt <= f_clk_cnt +1;
    if (f_clk_cnt == 5)
        // below cover statement is a simple alternative to testbench
        cover((counter == (HALF_CLOCK_STRECH-1)) && o_clk);

This kind of simple functional verification provides the designer with more confidence before even writing proper testbenches.

You can find the current working (VSCode) project here:

My Verilog Workflow – I

After reading this post, see

I just started learning Verilog and FPGA design and trying to come up with a workflow that can enhance my overall learning process. I am using this blog post to record this flow which may be helpful for others as well.

In general, I do not use closed-source/proprietary software. However, it seems FPGA development using completely opensource tools may not be possible at this moment! So, I decided to use a combination of open and closed source tools (albeit all of them are free as in free beer) to start my work.

By the way, if you have just started learning FPGA design like me, DON’T MISS Dan Gisselquist‘s ZipCPU blog, probably THE BEST online resource for learning Verilog!

Editor/IDE (Sublime Text)

Choosing an editor/IDE is important for any programming. This is especially true for Verilog programming as the built-in editors that come with Vivado or Quartus are almost useless. That is the reason why these tools allow the user to choose his/her external preferred editor. Over the years, I have tried many editors to see which suits my needs better. EclipseGeanySublime TextAtomVSCode, to name a few. Finally, I have decided to go with Sublime Text mainly because of the following reasons:

  • first and foremost, Sublime is a very lightweight application
  • using packages/plugins, Sublime can be configured as an IDE for almost any language you can think of

FSM Design Tool (Fizzim)

Whether you are designing an MCU based embedded system or an FPGA based digital system, partitioning the design using FSM methodology is a must. For embedded systems, I prefer to use tools such as SMC+QFSM and Ragel. Similarly, for digital systems, Fizzim is a good FSM design tool. As I said, I am a newbie as far as Verilog coding is concerned. So, I tried to use Fizzim to design a simple UART controller to understand it’s abilities. What I have noticed is, Fizzim is a translator for your thought process. It not only helps you visualize the problem but also in visualizing the code that is going to be generated. You know exactly how your output will look like during the “drawing” stage itself. By the way, Fizzim’s tutorial is a very good place for understanding FSM concepts (don’t miss the references section). Below is a screenshot of a UART controller that I designed using fizzim.


And code generated by fizzim can be found here. I have customized ‘‘ to format the code for my liking.


  1. Install the following tools (I am using Lubuntu 18.04):
    1. Fizzim (you need JRE for running the downloaded .jar file)
    2. Verilator
    3. g++ (might have come pre-installed with your OS)
    4. SymbiYosys
  2. Install the following sublime packages for linting purposes
    1. SublimeLinter-gcc
    2. Sublime​Linter-contrib-verilator
  3. Create/open a project in Sublime Text (use this Github repo as a template to start with)
  4. Configure file and press ctrl+shift+b (and select fizzim build) to generate Verilog code from Fizzim file, txuart2.fzm. This should generate/update txuart2.v file in the rtl folder.
  5. Change TOPMOD in rtl/Makefile file
  6. Exclude .cpp files which are not required in bench/cpp/CMakeLists.txt file
  7. Now, again press ctrl+shift+b (and select verilog build) which does the following sequentially:
    1. generate .cpp files in bench/cpp/lib folder using Verilator
    2. build testbench written in C++ using g++ (generated files are inside bench/cpp/build folder)
    3. run the output file (executable) generated in the bench/cpp/build folder
  8. If you have generated a .vcd file using your C++ testbench, then open it using GTKWave.
  9. All the above steps take care of simulation and verification aspects. For synthesizing, timing analysis, etc., you need a Quartus project to which you can link Verilog files that we created in the rtl folder. This Quartus project is placed inside qproj folder.
  10. That’s all. Now, you start improvising.

A few more Screenshots

Sublime Text with SystemVerilog package


Code generation using Fizzim


You can add “user code” to the generated Verilog file (incremental generation)


Configuring make files


C++ linting using SublimeLinter-gcc

cpp lint

Viewing generated trace file in GTKWave


Linking Sublime Text to Quartus


List of packages that I am currently using (my user settings can be found here)



It has been three years since my last post …

After finishing Ph.D., I worked in academia for ∼ 6 years before moving to industry. The main reason for me to leave academia was the “publish or perish” mentality that is prevalent these days in academia. I would rather enjoy the pressure of “design or perish” … 🙂

Anyway, for the past 3 years, I have been working at HBL Power Systems Ltd., Hyderabad, looking after the design of various RF and Communication Systems. I will always be indebted to HBL for providing me a lifetime opportunity to work on things that I would cherish for the rest of my life. Though I enjoyed my work at HBL, I felt like being consumed by work. I guess it has something to do with my greed for more knowledge. So, I decided to take a break from my regular work and spend more time with family. Also, I would like to use this time to work on some of my pet projects on which I couldn’t spend much time before.

For the past three years, I couldn’t post here because I was working for HBL. Now that I am free, I am going to resume my regular postings. My next post is going to be about an open-source “Verilog workflow” that I have been working on these days.

GUI version of Arraytool

For a long time, I have been thinking about creating a GUI application based on the Arraytool package that I have created many years back. Finally, I was able to spend some time on creating the application’s GUI layout and here is how it looks:


Not bad right? I used PySide to create this GUI layout. Now, all I need to do is to connect the GUI widgets to the original Arraytool package. You can find the corresponding source code here:

Source Files for all the Teaching Material that I have Developed

I have taught eight different courses so far and spent lot of time on preparing teaching material for these courses :(. You can already find some of this material on my “Teaching” page. However, those files are PDF files and you won’t be able to edit them according to your requirements. So, I am sharing the source files too in this post. You will find all the files (e.g., Lyx files, SVG files, etc.) here:

Now, you can edit these files to your taste. Happy LaTeXing!